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[Other resource] sdramusevhdl

Description: sdram的vhdl实现 本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
Platform: | Size: 84842 | Author: cxr | Hits:

[Other resource] sdram_control

Description: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Platform: | Size: 340592 | Author: 李伟 | Hits:

[Other resource] AlteraSDRAMControllerWhitePaper

Description: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Platform: | Size: 702000 | Author: wood | Hits:

[Other resource] xilinxSynthesizableHighPerformanceSDRAMController.

Description: xilinx的SDRAM控制器的白皮书，很详细的-xilinx SDRAM controller of the White Paper, detailed
Platform: | Size: 69036 | Author: wood | Hits:

[Other] lattice_sdram_source_code

Description: lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Platform: | Size: 32502 | Author: dido wang | Hits:

[Other resource] CommandResponse

Description: verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
Platform: | Size: 1244 | Author: hanjian | Hits:

[Other resource] SRAM_2

Description: FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
Platform: | Size: 554116 | Author: zlw | Hits:

[Other resource] sdr_sdram

Description: 详细的SDRAM控制器HDL代码，最顶层代码，很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
Platform: | Size: 2941 | Author: 陈建勇 | Hits:

[Other resource] sdr_data_path

Description: SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Platform: | Size: 1955 | Author: 陈建勇 | Hits:

[Other resource] Params

Description: SDRAM控制器Verilog员代码，设计参数模块，整个模块的所有参数定义-SDRAM controller member Verilog code, design parameter module, the entire module of all parameters defined
Platform: | Size: 849 | Author: 陈建勇 | Hits:

[Other resource] control_interface

Description: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Platform: | Size: 3410 | Author: 陈建勇 | Hits:

[Other resource] Commandinterface

Description: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Platform: | Size: 7694 | Author: 陈建勇 | Hits:

[Other resource] P4_PPC_SDRAM_Reference_Design

Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
Platform: | Size: 33819 | Author: 庞志勇 | Hits:

[Other resource] xapp134_vhdl

Description: The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
Platform: | Size: 2628213 | Author: ronsullivan | Hits:

[Other resource] SDRAM

Description: ALTERA SDR AM Controller White Paper
Platform: | Size: 658903 | Author: 付茗 | Hits:

[Other resource] sdram

Description: sdram test controller altera
Platform: | Size: 1520122 | Author: yangchun | Hits:

[Software Engineering] SDRAMController

Description: SDRAM Controller 设计详细文档 ，很有参考价值！
Platform: | Size: 446715 | Author: 王一 | Hits:

[Other] S3C44B0X中文技术文档

Description:

 

介    绍
三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。
S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch general DMAs / 2-ch peripheral DMAs with external request pins； External memory controller (chip select logic, FP/ EDO/SDRAM controller)； 5-ch PWM timers & 1-ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8-ch external interrupt source； RTC with calendar function； 8-ch 10-bit ADC； 1-ch multi-master IIC-BUS controller； 1-ch IIS-BUS controller； Sync. SIO interface and On-chip clock generator with PLL.。
S3C44B0X采用一种新的三星ARM CPU嵌入总线结构-SAMBA2，最大达66MHZ。

Platform: | Size: 78690 | Author: ssunshine | Hits:

[VHDL-FPGA-Verilog] ARM9_instruction_cache_verilogCodes

Description: Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
Platform: | Size: 3072 | Author: 杨力 | Hits:

[File Format] DDR_SDRAM_use_in_embedded

Description: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Platform: | Size: 237568 | Author: joucan | Hits:
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